$ gunzip -c urjtag-0.10.tar.gz | tar -xvf -
$ cd urjtag-0.10
$ ./configure
$ make
$ sudo make install
jtag> cable DLC5 ppdev /dev/parport0
Initializing ppdev port /dev/parport0
Could not open port /dev/parport0: Permission denied
Error: Cable initialization failed!
$ sudo chmod a+rw /dev/parport0
jtag> cable DLC5 ppdev /dev/parport0
Initializing ppdev port /dev/parport0
jtag> detect
Warning: TDO seems to be stuck at 1
jtag> cable ByteBlaster ppdev /dev/parport0
Initializing ppdev port /dev/parport0
jtag> detect
jtag> cable ByteBlaster ppdev /dev/parport0
Initializing ppdev port /dev/parport0
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00101001010100000100000010010011 (0x0000000029504093)
Manufacturer: Xilinx
Unknown part!
chain.c(149) Part 0 without active instruction
chain.c(200) Part 0 without active instruction
chain.c(149) Part 0 without active instruction
jtag> cable DLC5 ppdev /dev/parport0
Initializing ppdev port /dev/parport0
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00101001010100000100000010010011 (0x0000000029504093)
Manufacturer: Xilinx
Unknown part!
chain.c(149) Part 0 without active instruction
chain.c(200) Part 0 without active instruction
chain.c(149) Part 0 without active instruction
jtag> bsdl dump xc9572_pc44.bsd
signal VSSIO_2
signal VSSIO_1
signal VSSINT_1
signal VCCIO_1
:
中略
:
bit 210 C 0 *
bit 215 O ? *
bit 214 O ? *
bit 213 O ? *
$ bsdl2jtag xc9572_pc44.bsd xc9572_pc44
attribute IDCODE_REGISTER of xc9572_pc44 : entity is
"XXXX" & -- version
"1001010100000100" & -- part number
"00001001001" & -- manufacturer's id
"1"; -- required by standard
1001010100000100 xc9572_pc44 xc9572_pc44
0010 xc9572_pc44 2
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00101001010100000100000010010011 (0x0000000029504093)
Manufacturer: Xilinx
Part(0): xc9572_pc44
Stepping: 2
Filename: /usr/local/share/urjtag/xilinx/xc9572_pc44/xc9572_pc44
constant pc44: PIN_MAP_STRING:=
"PB00_01:1," &
"PB00_04:2," &
"PB00_05:3," &
"PB00_07:4," &
:
中略
:
"PB03_10:28," &
"PB03_13:29," &
"PB03_14:33," &
"PB03_16:34," &
"TCK:17," &
"TDI:15," &
"TDO:30," &
"TMS:16," &
"VCCINT_1:21," &
"VCCINT_VPP:41," &
"VCCIO_1:32," &
"VSSINT_1:23," &
"VSSIO_1:10," &
"VSSIO_2:31";
attribute BOUNDARY_LENGTH of xc9572_pc44 : entity is 216;
attribute BOUNDARY_REGISTER of xc9572_pc44 : entity is
" 2 (BC_1, *, internal, X)," &
" 1 (BC_1, *, internal, X)," &
" 0 (BC_1, *, internal, X)," &
" 5 (BC_1, PB03_16, input, X)," &
" 4 (BC_1, PB03_16, output3, X, 3, 0, Z)," &
" 3 (BC_1, *, controlr, 0)," &
" 8 (BC_1, *, internal, X)," &
" 7 (BC_1, *, internal, X)," &
" 6 (BC_1, *, internal, X)," &
:
中略
:
" 208 (BC_1, *, internal, X)," &
" 207 (BC_1, *, internal, X)," &
" 212 (BC_1, PB00_01, input, X)," &
" 211 (BC_1, PB00_01, output3, X, 210, 0, Z)," &
" 210 (BC_1, *, controlr, 0)," &
" 215 (BC_1, *, internal, X)," &
" 214 (BC_1, *, internal, X)," &
" 213 (BC_1, *, internal, X)";
" 212 (BC_1, PB00_01, input, X)," &
" 211 (BC_1, PB00_01, output3, X, 210, 0, Z)," &
" 210 (BC_1, *, controlr, 0)," &
PIN | SIGNAL | IN | OUT | CONT | CONNECT | REG | |
---|---|---|---|---|---|---|---|
1 | PB00_01 | 212 | 211 | 210 | A8 | 70 | 1 |
2 | PB00_04 | 203 | 202 | 201 | A9 | 67 | 4 |
3 | PB00_05 | 200 | 199 | 198 | A11 | 66 | 5 |
4 | PB00_07 | 194 | 193 | 192 | /OE | 64 | 7 |
5 | PB00_08 | 191 | 190 | 189 | A10 | 63 | 8 |
6 | PB00_10 | 185 | 184 | 183 | /CE | 61 | 10 |
7 | PB00_13 | 176 | 175 | 174 | CLK | 58 | 13 |
8 | PB00_14 | 173 | 172 | 171 | OUT2 | 57 | 14 |
9 | PB00_16 | 167 | 166 | 165 | OUT | 55 | 16 |
35 | PB01_01 | 158 | 157 | 156 | A7 | 52 | 19 |
36 | PB01_04 | 149 | 148 | 147 | A12 | 49 | 22 |
37 | PB01_05 | 146 | 145 | 144 | A15 | 48 | 23 |
38 | PB01_07 | 140 | 139 | 138 | A16 | 46 | 25 |
39 | PB01_08 | 137 | 136 | 135 | /RES | 45 | 26 |
40 | PB01_10 | 131 | 130 | 129 | /WE | 43 | 28 |
42 | PB01_13 | 122 | 121 | 120 | A17 | 40 | 31 |
43 | PB01_14 | 119 | 118 | 117 | A14 | 39 | 32 |
44 | PB01_16 | 113 | 112 | 111 | A13 | 37 | 34 |
11 | PB02_01 | 104 | 103 | 102 | NC | 34 | 37 |
12 | PB02_04 | 95 | 94 | 93 | DQ7 | 31 | 40 |
13 | PB02_07 | 86 | 85 | 84 | DQ6 | 28 | 43 |
14 | PB02_08 | 83 | 82 | 81 | DQ5 | 27 | 44 |
18 | PB02_10 | 77 | 76 | 75 | DQ4 | 25 | 46 |
19 | PB02_13 | 68 | 67 | 66 | DQ3 | 22 | 49 |
20 | PB02_14 | 65 | 64 | 63 | DQ2 | 21 | 50 |
22 | PB02_16 | 59 | 58 | 57 | DQ1 | 19 | 52 |
24 | PB03_01 | 50 | 49 | 48 | DQ0 | 16 | 55 |
25 | PB03_04 | 41 | 40 | 39 | A0 | 13 | 58 |
26 | PB03_07 | 32 | 31 | 30 | A1 | 10 | 61 |
27 | PB03_08 | 29 | 28 | 27 | A2 | 9 | 62 |
28 | PB03_10 | 23 | 22 | 21 | A3 | 7 | 64 |
29 | PB03_13 | 14 | 13 | 12 | A4 | 4 | 67 |
33 | PB03_14 | 11 | 10 | 9 | A5 | 3 | 68 |
34 | PB03_16 | 5 | 4 | 3 | A6 | 1 | 70 |
instruction IDCODE
jtag> shift ir
jtag> shift dr
jtag> dr
00101001010100000100000010010011
jtag> instruction SAMPLE/PRELOAD
jtag> shift ir
jtag> shift dr
jtag> dr
100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100
jtag> instruction EXTEST
jtag> shift ir
jtag> dr 100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100100
jtag> shift dr
$ jtag extest_script
Initializing ppdev port /dev/parport0
IR length: 8
Chain length: 1
Device Id: 00101001010100000100000010010011 (0x0000000029504093)
Manufacturer: Xilinx
Part(0): xc9572_pc44
Stepping: 2
Filename: /usr/local/share/urjtag/xilinx/xc9572_pc44/xc9572_pc44
Warning: line 5 exceeds 100 characters, clipped
dr: register length mismatch
$ jtag extest_script
Initializing ppdev port /dev/parport0
IR length: 8
Chain length: 1
Device Id: 00101001010100000100000010010011 (0x0000000029504093)
Manufacturer: Xilinx
Part(0): xc9572_pc44
Stepping: 2
Filename: /usr/local/share/urjtag/xilinx/xc9572_pc44/xc9572_pc44
100101100100101101100101101100101100100111101100101100100101100100101101100101101100111100100101101100101100100100100100101100100101101100101100100101101100101100100101100100101100100101101100101100100101101100101100
cable ByteBlaster ppdev /dev/parport0
detect
instruction EXTEST
shift ir
dr 100101100100101101100101101100101100100111101100101100100101100100101101100101101100111100100101101100101100100100100100101100100101101100101100100101101100101100100101100100101100100101101100101100100101101100101100
shift dr
usleep 1000000
instruction EXTEST
shift ir
dr 100101100100101101100101101100101100100101111100101100100101100100101101100101101100111100100101101100101100100100100100101100100101101100101100100101101100101100100101100100101100100101101100101100100101101100101100
shift dr
usleep 1000000
instruction EXTEST
shift ir
dr 100101100100101101100101101100101100100101101100111100100101100100101101100101101100111100100101101100101100100100100100101100100101101100101100100101101100101100100101100100101100100101101100101100100101101100101100
shift dr
usleep 1000000
instruction EXTEST
shift ir
dr 100101100100101101100101101100101100100101101100101100100101100100101101100101111100111100100101101100101100100100100100101100100101101100101100100101101100101100100101100100101100100101101100101100100101101100101100
shift dr
usleep 1000000
sub header {
print "cable ByteBlaster ppdev /dev/parport0\n";
print "detect\n";
print "\n";
}
sub xxx {
($x) = @_;
if ($x==0) {$line .= "101";} # set 0
elsif ($x>0) {$line .= "111";} # set 1
else {$line .= "100";} # Hi-Z
}
sub set_data {
$line = "";
&xxx(-1);
&xxx($ADRS&0x00100); #A8
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x00200); #A9
&xxx($ADRS&0x00800); #A11
&xxx(-1);
&xxx($oen); #/OE
&xxx($ADRS&0x00400); #A10
&xxx(-1);
&xxx($CEN); #/CE
&xxx(-1);
&xxx(-1);
&xxx($CLK); #CLK
&xxx($TRIG); #TRIGOUT
&xxx(-1);
&xxx($OUT); #STREAMOUT
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x00080); #A7
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x01000); #A12
&xxx($ADRS&0x08000); #A15
&xxx(-1);
&xxx($ADRS&0x10000); #A16
&xxx($RESN); #/RES
&xxx(-1);
&xxx($WEN); #/WE
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x20000); #A17
&xxx($ADRS&0x04000); #A14
&xxx(-1);
&xxx($ADRS&0x02000); #A13
&xxx(-1);
&xxx(-1);
&xxx(-1); #NC
&xxx(-1);
&xxx(-1);
&xxx($DATA&0x80); #DQ7
&xxx(-1);
&xxx(-1);
&xxx($DATA&0x40); #DQ6
&xxx($DATA&0x20); #DQ5
&xxx(-1);
&xxx($DATA&0x10); #DQ4
&xxx(-1);
&xxx(-1);
&xxx($DATA&0x08); #DQ3
&xxx($DATA&0x04); #DQ2
&xxx(-1);
&xxx($DATA&0x02); #DQ1
&xxx(-1);
&xxx(-1);
&xxx($DATA&0x01); #DQ0
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x00001); #A0
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x00002); #A1
&xxx($ADRS&0x00004); #A2
&xxx(-1);
&xxx($ADRS&0x00008); #A3
&xxx(-1);
&xxx(-1);
&xxx($ADRS&0x00010); #A4
&xxx($ADRS&0x00020); #A5
&xxx(-1);
&xxx($ADRS&0x00040); #A6
&xxx(-1);
}
sub extest {
($ADRS,$DATA,$CEN,$OEN,$WEN) = @_;
&set_data;
print "instruction EXTEST\n";
print "shift ir\n";
print "dr $line\n";
print "shift dr\n";
print "usleep 1000\n";
print "\n";
}
sub write_mem {
($A,$D) = @_;
&extest(0x5555,0xAA,0,1,1);
&extest(0x5555,0xAA,0,1,0);
&extest(0x2AAA,0x55,0,1,1);
&extest(0x2AAA,0x55,0,1,0);
&extest(0x5555,0xA0,0,1,1);
&extest(0x5555,0xA0,0,1,0);
&extest($A,$D,0,1,1);
&extest($A,$D,0,1,0);
&extest($A,$D,0,1,1);
}
$ADRS = 0;
$DATA = 0;
$CEN = 0;
$OEN = 0;
$WEN = 1;
$CLK = 0;
$TRIG = 0;
$OUT = 0;
$RESN = 1;
&header;
&write_mem(0,0);
&write_mem(1,1);
&write_mem(2,2);
&write_mem(3,3);
end;